RISC-V 32-bit Single Cycle Processor2026
This is a single-cycle 32-bit RISC-V processor (RV32I) built in SystemVerilog, to get hands-on experience with computer architecture, datapath routing, and RTL.
I2C Master Controller2026
Wrote an FSM to convert simple Read/Write commands into standard I2C conditions. Used tri-state logic (inout ports) to correctly control the bidirectional open-drain SDA line.
SPI Master2026
Built a parameterized SPI Master (Mode 0) supporting continuous back-to-back data transfers with automated CS pulsing and a synchronous reset state to handle interrupted transfers.
UART Transceiver2026
Developed a UART transmitter and receiver module in Verilog incorporating parity checking for error detection. Built a custom baud-rate generator and verified logic via GTKWave.
USB-to-UART PCB2026
Designed a 2-layer PCB to connect USB with microcontrollers. Incorporated a CH340G bridge, crystal oscillator, and voltage regulation. Generated fab-ready Gerbers passing DRC.
Synchronous FIFO2026
A simple synchronous FIFO implemented in System Verilog,along with testbench
GYANSUTRA2025-2026
The website version of the GYANSUTRA PDF hosted by Nakshatra - The Astronomy and Mathematics Society of NSUT
Configurable Traffic Light Controller2026
Designed a Moore FSM based traffic light controller with programmable timing inputs Implemented a parameterized 1-second timebase without gated clocks Generated RTL schematics using Vivado Tool Used: Vivado 2025.2
ESP Connect2025
A React Native app that can connect to ESP32 using Bluetooth Classic to send and receive messages.